1. Field of the Invention
The present invention is related to methods for handling system management interrupts in a multiprocessor system.
2. Background of the Related Art
Since the 386SL processor was introduced by the Intel Corporation, SMM has been available on IA32 processors as an execution mode hidden to operating systems that executes code loaded by BIOS or firmware. SMM is a special-purpose operating mode provided for handling system-wide functions like power management, system hardware control, or proprietary OEM-designed code. The execution mode is deemed “hidden” because the operating system (OS) and software applications cannot see it, or even access it.
IA32 processors are enabled to enter SMM via activation of an SMI (System Management Interrupt) signal. A similar signal called the PMI (Processor Management Interrupt) signal that is roughly analogous to the SMI signal is used for Itanium.™-class processors. For simplicity, both SMI and PMI signals are sometimes referred to as xMI signals herein. There is also an interrupt message type called “SMI” or “PMI” that use the APIC/XAPIC IA32 memory-mapped delivery mechanism or the IPF SAPIC delivery mechanism.
The processor architecture of a computer system will typically support several types of interrupts. An interrupt is a notification given to the processor that causes the processor to halt the execution of code such as operating code and handle a condition that has arisen in the system or in one of the system's external devices. As an example, when a key is pressed on the keyboard, an interrupt is passed to the processor from the peripheral controller. The interrupt causes the processor to momentarily stop its current execution stream and receive data from the peripheral controller. Another type of interrupt is a system management interrupt (SMI). Typically, a SMI is the highest priority non-maskable interrupt that can be issued in a computer system. A SMI is often issued when it is necessary for the processor to handle an error condition in the computer system.
When a system management interrupt is issued to the processor, the processor enters system management mode. In a multiple processor environment, because every processor receives the system management interrupt, each of the processors of the computer system will enter system management mode. As part of system management mode, each processor of the system is allocated a memory block of random access memory (RAM). This memory space is known as system management RAM or SMRAM. Upon entering system management mode, each processor saves the contents of its registers to its block of allocated SMRAM space. In addition, the contents of SMRAM will also include the operating code used by each processor's SMI handler.
Placing the processor in system management mode frees the processor from the exclusive control of the operating system. Because the processor is able to operate independently of the operating system, privileged level functions of the processor, including some memory and I/O functions, are no longer under the exclusive control of the operating system. As a result, some processor level functions can be manipulated by the application program by invoking the processor's system management mode and the routines of the SMI handler or the processor.
In multiple processor computer systems, the time required for the handling of a system management interrupt is influenced by the amount of time spent saving processor information to and restoring processor information from the SMRAM associated with each processor. Typically, in a multiple processor computer system, each processor of the computer system will enter a system management interrupt mode, even though only one processor of the computer system will be selected to actually handle the processing associated with the system management interrupt. As such, in a multiprocessor system, each processor must have control of the processor bus and access to system memory in order to enter into and exit from the system management interrupt mode. Because each processor typically attempts to enter into and exit from system management interrupt mode at the same time, the processors typically contend for control of the processor bus and access to memory. Because only one processor may use the processor bus at a time, the processors are unlikely to enter or exit SMM at the same time.
The SMI handler associated with any particular processor can only handle one current SMI event and latch one pending SMI event. If multiple SMI events are received when one or more processors are in SMI and one or more other processors are not in SMI, then certain processors may loose an SMI. This is because the processors in SMI keep the first SMI pending & discard the others, while the processors not in SMI enter the SMM due to the first SMI, keep the second SMI pending & discard the others. So, processors that loose an SMI may eventually exit the SMI handler before the rest of the processors. This causes a problem, because the processors remaining in the SMI handler need to process an SMI, but can't do so without all of the active processors in SMI. Essentially, the latency between multiple processors entering and exiting SMM can cause difficulties in handling multiple SMI events.
Therefore, there is a need for an improved method for handling multiple SMI events in a multiprocessor system. It would be desirable if the method would detect a lost SMI event and recover the lost SMI so that it can be handled appropriately. It would be further desirable if the method could be applied to multiprocessor systems having any number of processors.